Type Members

1.  case class Axi4Master(axi: Axi4, clockDomain: ClockDomain, name: String = "unnamed") extends Product with Serializable

   Simulation master for the Axi4 bus protocol spinal.lib.bus.amba4.axi.Axi4.

   Simulation master for the Axi4 bus protocol spinal.lib.bus.amba4.axi.Axi4.

   axi

   bus master to drive

   clockDomain

   clock domain to sample data on

   Example:

   1. SimConfig.compile(new Component {
        val io = new Bundle {
          val axiSlave = slave(Axi4(Axi4Config(32, 32)))
        }
        io.axiSlave.assignDontCare
      }).doSim("sample") { dut =>
        val master = Axi4Master(dut.io.axiSlave, dut.clockDomain)
        val data = master.read(0x1000, 4)
      }

2.  abstract class Axi4ReadOnlyMasterAgent extends AnyRef
3.  abstract class Axi4ReadOnlyMonitor extends AnyRef
4.  class Axi4ReadOnlySlaveAgent extends AnyRef
5.  abstract class Axi4WriteOnlyMasterAgent extends AnyRef
6.  abstract class Axi4WriteOnlyMonitor extends AnyRef
7.  class Axi4WriteOnlySlaveAgent extends AnyRef
8.  case class AxiJob(address: Long, burstLength: Int, burstSize: Int, burstType: Int, id: Long) extends Product with Serializable
9.  case class AxiMemorySim(axi: Axi4, clockDomain: ClockDomain, config: AxiMemorySimConfig) extends Product with Serializable
10.  case class AxiMemorySimConfig(maxOutstandingReads: Int = 8, maxOutstandingWrites: Int = 8, readResponseDelay: Int = 0, writeResponseDelay: Int = 0, interruptProbability: Int = 0, interruptMaxDelay: Int = 0, defaultBurstType: Int = 1, useAlteraBehavior: Boolean = false) extends Product with Serializable

    Configuration class for the AxiMemorySim.

    Configuration class for the AxiMemorySim.

    useAlteraBehavior

    Couple write command and write channel as in the Altera Cyclone 5 F2H_SDRAM port.

11.  class MemoryPage extends AnyRef
12.  case class SparseMemory() extends Product with Serializable