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  • package root
    Definition Classes
    root
  • package vexiiriscv
    Definition Classes
    root
  • package test
    Definition Classes
    vexiiriscv
  • class VexiiRiscvProbe extends AnyRef

    VexiiRiscvProbe can be used in a simulation to probe the activities of VexiiRiscv and notifies a list of TraceBackend with what happened (ex commit, memory load, memory store, trap, ...)

    VexiiRiscvProbe can be used in a simulation to probe the activities of VexiiRiscv and notifies a list of TraceBackend with what happened (ex commit, memory load, memory store, trap, ...)

    There is a few usefull backends : - RVLS to check that the simulated VexiiRiscv CPU is doing things right - A file backend, to keep a text file trace of what happened (instead of having to look into a waveform)

    It also keep a trace of various performance metrics, as the IPC, branch miss rate, ...

    Definition Classes
    test
  • DecodeCtx
  • FetchCtx
  • HartCtx
  • JbStats
  • MicroOpCtx
  • ProbeTraceIo

class FetchCtx extends AnyRef

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  1. new FetchCtx()

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