Packages

  • package root
    Definition Classes
    root
  • package vexiiriscv
    Definition Classes
    root
  • package test
    Definition Classes
    vexiiriscv
  • class VexiiRiscvProbe extends AnyRef

    VexiiRiscvProbe can be used in a simulation to probe the activities of VexiiRiscv and notifies a list of TraceBackend with what happened (ex commit, memory load, memory store, trap, ...)

    VexiiRiscvProbe can be used in a simulation to probe the activities of VexiiRiscv and notifies a list of TraceBackend with what happened (ex commit, memory load, memory store, trap, ...)

    There is a few usefull backends : - RVLS to check that the simulated VexiiRiscv CPU is doing things right - A file backend, to keep a text file trace of what happened (instead of having to look into a waveform)

    It also keep a trace of various performance metrics, as the IPC, branch miss rate, ...

    Definition Classes
    test
  • DecodeCtx
  • FetchCtx
  • HartCtx
  • JbStats
  • MicroOpCtx
  • ProbeTraceIo

class HartCtx extends AnyRef

Linear Supertypes
AnyRef, Any
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  1. HartCtx
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Visibility
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Instance Constructors

  1. new HartCtx(hartId: Int)

Value Members

  1. def add(tracer: TraceBackend): Unit
  2. val branchStats: JbStats
  3. def close(): Unit
  4. var commits: Long
  5. val decode: Array[DecodeCtx]
  6. val fetch: Array[FetchCtx]
  7. val hartId: Int
  8. val jbStats: HashMap[Long, JbStats]
  9. val konataThread: Option[Thread]
  10. var lastCommitAt: Long
  11. var lastUopId: Long
  12. val microOp: Array[MicroOpCtx]
  13. var microOpAllocPtr: Int
  14. var microOpRetirePtr: Int