NaxRiscv
  • Introduction
    • NaxRiscv
      • Project development and status
      • Why a OoO core targeting FPGA
      • Additional resources
    • Pipeline
    • How to use
    • Hardware description
    • Acknowledgment
    • Funding
  • Frontend
    • Decoder
    • Physical register allocation
    • Architectural to physical
    • Physical to ROB ID
    • Dispatch / Issue
  • Execution units
    • Custom instruction
      • SIMD add
        • Plugin implementation
        • NaxRiscv generation
        • Software test
        • Simulation
        • Conclusion
        • Hardcore way
  • Memory system
    • Load store unite
    • MMU
    • Coherency
    • L2 cache
  • Branch prediction
    • Fetch prediction
    • Decode prediction
    • Jump/branch circular buffer
  • Backend
    • Commit
    • Register file
      • Dual-port based
      • Latch based
  • Simulation
    • Introduction
    • Spike
    • Multi core simulation
  • Performance and Area
    • RV32
    • RV64
    • Notes
    • How to run the benchmark
  • Abstractions / HDL
    • Framework
      • Plugin tasks
      • Service definition
      • Service implementation
      • Service usage
      • Service Pipeline definition
      • Service Pipeline usage
      • Execution units
      • ShiftPlugin
    • Pipeline
    • State machine API
    • Automated multiport memory transformation
  • Misc
    • Jtag / OpenOCD / GDB
    • Security
      • Side channel attack
        • How to reproduce
  • Hardware
    • Litex
      • Digilent nexys video
      • Putting debian on the SDCARD
      • Generating everything from scratch
    • ASIC
      • Generating verilog
      • OpenRam
      • OpenLane
        • Setup / how to reproduce
        • Running simulation
        • Results
        • Issues
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