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Design errors

• Assignement overlap
  • Introduction
  • Example
• Clock crossing violation
  • Introduction
  • Example
    • crossClockDomain tag
    • setSyncronousWith
• Combinational loop
  • Introduction
  • Example
  • False-positive
• Hierarchy violation
  • Introduction
  • Example
• Io bundle
  • Introduction
  • Example
• Latch detected
  • Introduction
  • Example
• No driver on
  • Introduction
  • Example
• NullPointerException
  • Introduction
  • Example
• Register defined as component input
  • Introduction
  • Example
• Scope violation
  • Introduction
  • Example
• Spinal can’t clone class
  • Introduction
  • Example
• Unassigned register
  • Introduction
  • Example
  • Register with only init
• Unreachable is statement
  • Introduction
  • Example
• Width mismatch
  • Introduction
  • Assignement example
  • Operator example

Introduction

The SpinalHDL compile will perform many checks on your design to be sure that the generated VHDL/Verilog will be safe for simulation and synthesis. Basicaly, it should not be possible to generate a broken VHDL/Verilog. There is a none exaustive list of SpinalHDL checks :

• Assignement overlaping

• Clock crossing

• Hiearchy violation

• Combinatorial loops

• Latches

• Undrived signals

• Width missmatch

• Unreachable switch statements

On each SpinalHDL error report, you will find a stack trace which is realy usefull to accuratly findout where is the design error. It could look overkill in a first look, but as soon you start to go futher the traditional way of doing hardware description, it is realy a helpfull tool.