As always you can use your standard simulation tools to simulate the VHDL/Verilog generated out from SpinalHDL, but since SpinalHDL 1.0.0 the language integrate an API to write testbenches and test your hardware directly in Scala. This API provide the capabilities to read and write the DUT signals, fork and join simulation processes, sleep and wait until a given condition is filled.
How SpinalHDL simulate the hardware¶
This method has several advantage :
The C++ simulation model is realy fast to process simulation steps
It test the generated Verilog hardware instead of the SpinalHDL internal model
It doesn’t require SpinalHDL to be able itself to simulate the hardware (Less codebase, less bugs as Verilator is a reliable tool)
And some limitations :
Verilator will only accept to translate Synthetisable Verilog code