SpinalHDL
Foreword
Why moving away from traditional HDL
VHDL/Verilog aren’t Hardware Description Languages
Event driven paradigm doesn’t make any sense for RTL
Recent revisions of VHDL and Verilog aren’t usable
VHDL records, Verilog struct are broken (SystemVerilog is good on this, if you can use it)
VHDL and Verilog are so verbose
Meta Hardware Description capabilities
Introduction
About SpinalHDL
What is SpinalHDL?
What SpinalHDL is not
The Spinal development flow
Advantages of using SpinalHDL over VHDL / Verilog
A simple example
Component
Ports
Internal logic
Projects using SpinalHDL
Repositories
Companies
Getting in touch
License
Contributing
FAQ
What is the overhead of SpinalHDL generated RTL compared to human written VHDL/Verilog?
What if SpinalHDL becomes unsupported in the future?
Does SpinalHDL keep comments in generated VHDL/verilog?
Could SpinalHDL scale up to big projects?
How SpinalHDL came to be
Why develop a new language when there is VHDL/Verilog/SystemVerilog?
How to use an unreleased version of SpinalHDL (but committed on git)?
Other learning materials
Getting Started
Install and setup
Mandatory requirements
Installing SBT in an internet-free environment
Recommended requirements
Create a SpinalHDL project
The directory structure of a project
Using Spinal on SpinalHDL code
Using Spinal from CLI with SBT
Using Spinal from VSCodium
Using Spinal from IntelliJ IDEA
Scala Guide
Basics
Types
Variables
Functions
Object
Entry point (main)
Class
Templates / Type parameterization
Coding conventions
Introduction
class vs case class
Interaction
Introduction
How SpinalHDL works behind the API
Everything is a reference
Hardware types
Names of signals in the generated RTL
Scala is for elaboration, SpinalHDL for hardware description
Scala elaboration capabilities (if, for, functional programming)
Scala guide
Introduction
Help for VHDL people
VHDL comparison
Introduction
Process
Implicit vs explicit definitions
Clock domains
Component’s internal organization
Safety
Functions and procedures
Buses and Interfaces
Signal declaration
Component instantiation
Casting
Resizing
Parameterization
Meta hardware description
VHDL equivalences
Entity and architecture
Data types
Signal
Assignments
Literals
Registers
Process blocks
Cheatsheets
Core
Lib
Symbolic
Data types
Bool
Description
Declaration
Operators
Logic
Edge detection
Comparison
Type cast
Misc
MaskedBoolean
Bits
Description
Declaration
Operators
Logic
Comparison
Type cast
Bit extraction
Misc
MaskedLiteral
UInt/SInt
Description
Declaration
Operators
Logic
Arithmetic
Comparison
Type cast
Bit extraction
Misc
FixPoint operations
Lower bit operations
High bit operations
fixTo function
SpinalEnum
Description
Declaration
Encoding
Example
Operators
Comparison
Types
Type cast
Bundle
Description
Declaration
Conditional signals
Operators
Comparison
Type cast
Convert Bits back to Bundle
IO Element direction
in/out
master/slave
Vec
Description
Declaration
Examples
Operators
Comparison
Type cast
Misc
Lib helper functions
UFix/SFix
Description
Declaration
Unsigned Fixed-Point
Signed Fixed-Point
Format
Examples
Assignments
Valid Assignments
From a Scala constant
Raw value
Example
Operators
Arithmetic
Comparison
Type cast
Misc
Floating
Description
IEEE-754 floating format
Recoded floating format
Declaration
IEEE-754 Number
Recoded floating-point number
Operators
Type cast
AFix
Description
Declaration
Mathematical Operations
Inequality Operations
Bitshifting
Saturation and Rounding
Assignment
Introduction
Structuring
Component and hierarchy
Introduction
Input / output definition
Pruned signals
Parametrized Hardware (“Generic” in VHDL, “Parameter” in Verilog)
Synthesized component names
Area
Introduction
Function
Introduction
RGB to gray
Valid Ready Payload bus
Clock domains
Introduction
Instantiation
Configuration
Internal clock
External clock
Signal priorities in HDL generation
Context
Clock domain crossing
Special clocking Areas
Slow Area
BootReset
ResetArea
ClockEnableArea
Instantiate VHDL and Verilog IP
Description
Defining an blackbox
Generics
Instantiating a blackbox
Clock and reset mapping
io prefix
Rename all io of a blackbox
Add RTL source
VHDL - No numeric type
Preserving names
Introduction
Nameable base class
Name extraction from Scala
Area in a Component
Area in a function
Composite in a function
Composite chains
Composite in a Bundle’s function
Unamed signal handling
Verilog expression splitting
Verilog long expression splitting
When statement condition
In last resort
Parametrization
Introduction
Elaboration time parameters
Optional hardware
Semantic
Assignments
Assignments
Width checking
Combinatorial loops
When/Switch/Mux
When
Switch
Example
Additional options
Local declaration
Mux
Bitwise selection
Example
Rules
Introduction
Concurrency
Last valid assignment wins
Signal and register interactions with Scala (OOP reference + Functions)
Sequential logic
Registers
Introduction
Instantiation
Reset value
Initialization value for simulation purposes
Register vectors
Transforming a wire into a register
RAM/ROM
Syntax
Synchronous enable quirk
Read-under-write policy
Mixed-width ram
Automatic blackboxing
Blackboxing policy
Standard memory blackboxes
Design errors
Assignment overlap
Introduction
Example
Clock crossing violation
Introduction
Example
crossClockDomain tag
setSyncronousWith
BufferCC
Combinatorial loop
Introduction
Example
False-positives
Hierarchy violation
Introduction
Example
Io bundle
Introduction
Example
Latch detected
Introduction
Example
Due to mux
No driver on
Introduction
Example
NullPointerException
Introduction
Example
Issue explanation
Register defined as component input
Introduction
Example
Scope violation
Introduction
Example
Spinal can’t clone class
Introduction
Example 1
Example 2
Unassigned register
Introduction
Example
Register with only init
Unreachable is statement
Introduction
Example
Width mismatch
Introduction
Assignment example
Operator example
Introduction
Other language features
Utils
General
Cloning hardware datatypes
Passing a datatype as construction parameter
The old way
The safe way
Frequency and time
Binary prefix
Stub
Assertions
Report
ScopeProperty
Analog and inout
Introduction
Analog
inout
InOutWrapper
Manually driving Analog bundles
VHDL and Verilog generation
Generate VHDL and Verilog from a SpinalHDL Component
Parametrization from Scala
Parametrization from shell
Generated VHDL and Verilog
Organization
Combinational logic
Sequential logic
VHDL and Verilog attributes
Introduction
Introduction
Libraries
Utils
State less utilities
State full utilities
Counter
Timeout
ResetCtrl
Special utilities
Stream
Specification
Semantics
Functions
Utils
StreamFifo
StreamFifoCC
StreamCCByToggle
StreamWidthAdapter
StreamArbiter
StreamJoin
StreamFork
StreamMux
StreamDemux
StreamDispatcherSequencial
Simulation support
Flow
Specification
Functions
Code example
Fragment
Specification
Functions
State machine
Introduction
StateMachine
Entry point
Transitions
State encoding
States
StateDelay
StateFsm
StateParallelFsm
Notes about the entry state
VexRiscv (RV32IM CPU)
Bus Slave Factory
Introduction
Functionality
Fiber framework
Simple dummy example
Handle[T]
soon(handle)
BinarySystem
Specification
String to Int/Long/BigInt
Int/Long/BigInt to String
Int/Long/BigInt to Binary-List
Binary-List to Int/Long/BigInt
BigInt enricher
RegIf
Automatic allocation
28 Access Types
Automatic documentation generation
Example
Interrupt Factory
Interrupt Design Spec
IP level interrupt Factory
SYS level interrupt merge
Spinal Factory
Example
Developers Area
Bus
AHB-Lite3
Configuration and instanciation
Variations
Apb3
Introduction
Configuration and instanciation
Functions and operators
Axi4
Introduction
Configuration and instanciation
Variations
Functions and operators
AvalonMM
Introduction
Configuration and instanciation
Com
UART
Introduction
Bus definition
UartCtrl
USB device
Introduction
Architecture
Registers
Descriptors
Usage
USB OHCI
Introduction
Usage
IO
ReadableOpenDrain
ReadableOpenDrain
TriState
Introduction
TriState
TriStateArray
Graphics
Colors
RGB
VGA
VGA bus
VGA timings
VGA controller
EDA
QSysify
Introduction
Example
tags
Adding new interface support
QuartusFlow
Introduction
For a single rtl file
For an existing project
Misc
Plic Mapper
PlicMapper.apply
PlicMapping.sifive
PlicMapping.light
Introduction
Introduction
Simulation
Installation instructions
Scala
Backend-dependent installation instructions
Setup and installation of GHDL
Setup and installation of Icarus Verilog
VCS Simulation Configuration
Setup and installation of Verilator
Boot a simulation
Introduction
Configuration
Running multiple tests on the same hardware
Throw Success or Failure of the simulation from a thread
Accessing signals of the simulation
Read and write signals
Accessing signals inside the component’s hierarchy
Clock domains
Stimulus API
Wait API
Callback API
Default ClockDomain
New ClockDomain
Thread-full API
Fork and join simulation threads
Sleep and waitUntil
Thread-less API
Sensitive API
Simulation engine
Examples
Asynchronous adder
Dual clock fifo
Single clock fifo
Synchronous adder
Uart decoder
Uart encoder
Introduction
How SpinalHDL simulates the hardware with Verilator backend
How SpinalHDL simulates the hardware with GHDL/Icarus Verilog backend
How SpinalHDL simulates the hardware with Synopsys VCS backend
Performance
Formal verification
General
Formal backend
Installing requirements
Example
External assertions
Internal assertions
External stimulus
More assertions / past
Assuming memory content
Utilities and primitives
Assertions / clock / reset
Specifying the initial value of a signal
Specifying a initial assumption
Memory content (Mem)
Specifying assertion in the reset scope
Formal primitives
Limitations
Naming polices
For Component
For interfaces implement IMasterSlave
Examples
Simple ones
APB3 definition
Introduction
Specification
Implementation
Usage
Carry adder
Color summing
Counter with clear
PLL BlackBox and reset controller
The PLL BlackBox definition
TopLevel definition
RGB to gray
Sinus rom
Intermediates ones
Fractal calculator
Introduction
Specification
Elaboration parameters (Generics)
Bundle definition
Component implementation
UART
Specification
Data structures
Implementation
Simple usage
Example with test bench
Bonus: Having fun with Stream
VGA
Introduction
Data structures
VGA Controller
Advanced ones
JTAG TAP
Introduction
JTAG bus
JTAG state machine
JTAG TAP
Jtag instructions
User friendly wrapper
Usage demonstration
Memory mapped UART
Introduction
Specification
Implementation
Pinesec
Timer
Introduction
Timer
Bridging function
Introduction
Getting started
Legacy
RiscV
Features
Base FPGA project
How to generate the CPU VHDL
How to debug
Todo
pinsec
Hardware
Introduction
RISCV
AXI4
APB3
Generate the RTL
SoC toplevel (Pinsec)
Introduction
Defining all IO
Clock and resets
Main components
Peripherals
Bus interconnects
Misc
Introduction
Introduction
Board support
Software
RISCV tool-chain
OpenOCD/GDB/Eclipse configuration
Developers area
Bus Slave Factory Implementation
Introduction
Specification
Implementation
BusSlaveFactory
BusSlaveFactoryDelayed
AvalonMMSlaveFactory
Conclusion
How to HACK this documentation
Title convention
Wavedrom integration
New section
example
Build through Mill
Complie the library
Run all test suites
Run a specified test suite
Run a specified App
Publish locally
SpinalHDL internal datamodel
Introduction
General structure
Exploring the datamodel
Compilation Phases
Modifying a netlist as a user without plugins
User space netlist analysis
Enumerating every ClockDomain used
Types
Introduction
Bool
Declaration
Operators
The BitVector family - (
Bits
,
UInt
,
SInt
)
Declaration syntax
Operators
Masked comparison
Bits
UInt, SInt
Bool, Bits, UInt, SInt
Vec
Bundle
Simple example (RGB/VGA)
Interface example (APB)
Enum
Data (Bool, Bits, UInt, SInt, Enum, Bundle, Vec)
Literals as signal declaration
SpinalHDL
»
Examples
»
Advanced ones
»
Pinesec
View page source
Pinesec
¶
Remember to add it
Other Versions
v: v1.8.0
Tags
v1.3.1
v1.3.8
v1.5.0
v1.6.0
v1.8.0
Branches
dev
master
Downloads
HTML
PDF