常见错误
本页将讨论人们在使用 SpinalHDL 时可能出现的错误。
“main”线程中异常 java.lang.NullPointerException
控制台输出:
Exception in thread "main" java.lang.NullPointerException
代码示例:
val a = b + 1 // b can't be read at that time, because b isn't instantiated yet
val b = UInt(4 bits)
问题解释:
SpinalHDL 不是一种语言,它是一个 Scala 库,这意味着它遵循与 Scala 语言相同的通用规则。当您运行 SpinalHDL 硬件描述来生成相应的 VHDL/Verilog RTL 时,您的 SpinalHDL 硬件描述将作为 Scala 程序执行,并且执行程序到该行时, b 将是一个 null
空引用,这就是为什么你在这之前不能使用它的原因。
层次违例(Hierarchy violation)
SpinalHDL 编译器从层次结构的角度检查所有赋值是否合法。后续章节将详细阐述多个案例
Signal X can’t be assigned by Y
控制台输出:
Hierarchy violation : Signal X can't be assigned by Y
代码示例:
class ComponentX extends Component {
...
val X = Bool()
...
}
class ComponentY extends Component {
...
val componentX = new ComponentX
val Y = Bool()
componentX.X := Y // This assignment is not legal
...
}
class ComponentX extends Component {
val io = new Bundle {
val X = Bool() // Forgot to specify an in/out direction
}
...
}
class ComponentY extends Component {
...
val componentX = new ComponentX
val Y = Bool()
componentX.io.X := Y // This assignment will be detected as not legal
...
}
问题解释:
You can only assign input signals of subcomponents, else there is an hierarchy violation. If this issue happened, you probably forgot to specify the X signal’s direction.
Input signal X can’t be assigned by Y
控制台输出:
Hierarchy violation : Input signal X can't be assigned by Y
代码示例:
class ComponentXY extends Component {
val io = new Bundle {
val X = in Bool()
}
...
val Y = Bool()
io.X := Y // This assignment is not legal
...
}
问题解释:
You can only assign an input signals from the parent component, else there is an hierarchy violation. If this issue happened, you probably mixed signals direction declaration.
Output signal X can’t be assigned by Y
控制台输出:
Hierarchy violation : Output signal X can't be assigned by Y
代码示例:
class ComponentX extends Component {
val io = new Bundle {
val X = out Bool()
}
...
}
class ComponentY extends Component {
...
val componentX = new ComponentX
val Y = Bool()
componentX.X := Y // This assignment is not legal
...
}
问题解释:
You can only assign output signals of a component from the inside of it, else there is an hierarchy violation. If this issue happened, you probably mixed signals direction declaration.