This page only documents the first generation of RISC-V CPU created in SpinalHDL. This page does not document the VexRiscV CPU, which is the second generation of this CPU and is available here and offers better performance/area/features.
Pipelined on 5 stages (Fetch Decode Execute0 Execute1 WriteBack)
Multiple branch prediction modes : (disable, static or dynamic)
Data path parameterizable between fully bypassed to fully interlocked
One cycle multiplication
34 cycle division
Iterative shifter (N shift -> N cycles)
Single cycle shifter
Debugging module (with JTAG bridge, openOCD port and GDB)
Instruction cache with wrapped burst memory interface, one way
Data cache with instructions to evict/flush the whole cache or a given address, one way
Performance/Area (on cyclone II)
small core -> 846 LE, 0.6 DMIPS/Mhz
debug module (without JTAG) -> 240 LE
JTAG Avalon master -> 238 LE
big core with MUL/DIV/Full shifter/I$/Interrupt/Debug -> 2200 LE, 1.15 DMIPS/Mhz, at least 100 Mhz (with default synthesis option)
Base FPGA project
You can find a DE1-SOC project which integrate two instance of the CPU with MUL/DIV/Full shifter/I$/Interrupt/Debug there :
CPU/JTAG/VGA IP are pre-generated. Quartus Prime : 15.1.
How to generate the CPU VHDL
This avalon version of the CPU isn’t present in recent releases of SpinalHDL. Please consider the VexRiscv instead.
How to debug
You can find the openOCD fork here :
An example target configuration file could be find here :
Then you can use the RISCV GDB.
Optimise instruction/data caches FMax by moving line hit condition forward into combinatorial paths.
Contact firstname.lastname@example.org for more information