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Structuring

The chapters below explain:

• how to build reusable components

• alternatives to components to group hardware

• handling of clock/reset domains

• instantiation of existing VHDL and Verilog IP

• how names are assigned in SpinalHDL, and how naming can be influenced

• Components and hierarchy
  • Input / output definition
  • Pruned signals
  • Parametrized Hardware (“Generic” in VHDL, “Parameter” in Verilog)
  • Synthesized component names
• Area
• Function
  • RGB to gray
  • Valid Ready Payload bus
• Clock domains
  • Introduction
  • Instantiation
    • Configuration
    • Internal clock
    • External clock
    • Signal priorities in HDL generation
    • Context
  • Clock domain crossing
  • Special clocking Areas
    • Slow Area
    • BootReset
    • ResetArea
    • ClockEnableArea
• Instantiate VHDL and Verilog IP
  • Description
  • Defining an blackbox
  • Generics
  • Instantiating a blackbox
  • Clock and reset mapping
  • io prefix
  • Rename all io of a blackbox
  • Add RTL source
  • VHDL - No numeric type
• Preserving names
  • Nameable base class
  • Name extraction from Scala
  • Area in a Component
  • Area in a function
  • Composite in a function
  • Composite chains
  • Composite in a Bundle’s function
  • Unnamed signal handling
    • Verilog expression splitting
    • Verilog long expression splitting
    • When statement condition
    • In last resort
• Parametrization
  • Elaboration time parameters
  • Optional hardware