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JTAG

VexiiRiscv support debugging by implementing the official RISC-V debug spec.

• Compatible with OpenOCD (and maybe some other closed vendor, but untested)

• Can be used through a regular JTAG interface

• Can be used via tunneling through a single JTAG TAP instruction (FPGA native jtag interface)

• Support for some hardware trigger (PC, Load/Store address)