VexiiRiscv
  • Introduction
    • Other doc / media / talks
    • Glossary
    • Technicalities
    • About RISC-V
    • About VexRiscv (not VexiiRiscv)
    • Navigating the code
  • How to use
    • Environment (Dependencies)
      • Docker Container
      • Setup dependencies
      • Repo setup
    • Generate verilog
    • Run a simulation
    • Synthesis
    • Other resources
    • Using IntelliJ IDEA
      • Setup
      • Known issues
    • Using Konata
  • Self Contained Tutorial
    • Tooling
    • Assembler
      • Looking at examples
      • Write the assembler code
      • Build the assembler code
      • Initial run (Error)
      • Fixing the Error
      • The assembler "hello world"
      • Looking at the pipeline
      • Enabling branch prediction
      • Looking at the waveform
      • Introducing a bug
      • Experimenting with privilege levels
      • Connecting with openocd to the simulation
    • C code "hello world" (literally)
      • Write the C code
      • Compiling the Code
      • Compilation error
      • Running the code
      • Reading a CSR
  • Ready made Docker environment
    • Linux and MacOS X
    • Windows
    • Generating the verilog
    • Running a simulation
    • Opening the traces with GTKWave
    • Opening the traces with Konata
    • Opening Intellij IDEA
    • Shutting down the Container
    • Using the build environment
  • Framework
    • Tools and API
    • Scala / SpinalHDL
    • Plugin / Fiber / Retainer
      • Simple all-in-one example
      • Negotiation example
    • Database
    • Pipeline API
    • VexiiRiscv assumptions
  • Fetch
    • FetchPipelinePlugin
    • PcPlugin
    • FetchCachelessPlugin
    • FetchL1Plugin
    • PrefetcherNextLinePlugin
    • BtbPlugin
    • GSharePlugin
    • HistoryPlugin
  • Decode
    • DecodePipelinePlugin
    • AlignerPlugin
    • DecoderPlugin
    • DispatchPlugin
      • Architecture
      • Elaboration
  • Execute
    • Introduction
    • Plugins
      • Infrastructures
        • ExecutePipelinePlugin
        • ExecuteLanePlugin
        • RegFilePlugin
        • SrcPlugin
        • RsUnsignedPlugin
        • IntFormatPlugin
        • WriteBackPlugin
        • LearnPlugin
      • Instructions
        • IntAluPlugin
        • BarrelShifterPlugin
        • BranchPlugin
        • MulPlugin
        • DivPlugin
        • LsuCachelessPlugin
        • LsuPlugin
        • CsrAccessPlugin
        • EnvPlugin
    • Custom instruction
      • SIMD add
        • Plugin implementation
        • VexiiRiscv generation
        • Software test
        • Simulation
        • Conclusion
    • FPU
      • Plugins architecture
      • Area / Timings options
      • Optimized software
  • Branch
    • BtbPlugin
    • GSharePlugin
    • DecodePlugin
    • BranchPlugin
    • LearnPlugin
  • LSU / Memory
    • Without L1
    • With L1
      • Prefetching
        • PrefetchRptPlugin
        • performance measurements
      • Hardware Memory coherency
      • Atomic Memory Operation
      • Load Reserve / Store Conditional
      • Memory system
        • Why Tilelink
        • Efficiency cookbook
  • Privileges
    • CsrAccessPlugin
      • PrivilegedPlugin
      • CsrRamPlugin
      • TrapPlugin
      • PerformanceCounterPlugin
      • EnvPlugin
      • MmuPlugin
      • PmpPlugin
  • Debug support
    • Architecture
    • EmbeddedRiscvJtag
  • Performance / Area / FMax
    • Tuning
    • Critical paths tool
  • SoC
    • MicroSoc
      • Verilog generation
      • Simulation (SpinalSim / Verilator)
      • Compiling and running C/C++ with CMake
      • Adding a custom peripheral
      • Exporting an APB3 bus to the toplevel
      • Adding a custom instruction
    • Litex
VexiiRiscv
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Version: master (HEAD) git~50fa072 2025-03-17

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