VexiiRiscv
  • Introduction
    • Other doc / media / talks
    • Technicalities
    • Navigating the code
    • About RISC-V
    • About VexRiscv (not VexiiRiscv)
    • Check list
  • Framework
    • Tools and API
    • Scala / SpinalHDL
    • Plugin / Fiber / Retainer
      • Simple all-in-one example
      • Negotiation example
    • Database
    • Pipeline API
  • Fetch
    • FetchPipelinePlugin
    • PcPlugin
    • FetchCachelessPlugin
    • FetchL1Plugin
    • PrefetcherNextLinePlugin
    • BtbPlugin
    • GSharePlugin
    • HistoryPlugin
  • Decode
    • DecodePipelinePlugin
    • AlignerPlugin
    • DecoderPlugin
    • DispatchPlugin
      • Architecture
      • Elaboration
  • Execute
    • Introduction
    • Plugins
      • Infrastructures
        • ExecutePipelinePlugin
        • ExecuteLanePlugin
        • RegFilePlugin
        • SrcPlugin
        • RsUnsignedPlugin
        • IntFormatPlugin
        • WriteBackPlugin
        • LearnPlugin
      • Instructions
        • IntAluPlugin
        • BarrelShifterPlugin
        • BranchPlugin
        • MulPlugin
        • DivPlugin
        • LsuCachelessPlugin
        • LsuPlugin
      • Special
        • CsrAccessPlugin
        • CsrRamPlugin
        • PrivilegedPlugin
        • TrapPlugin
        • PerformanceCounterPlugin
        • EnvPlugin
    • Custom instruction
      • SIMD add
        • Plugin implementation
        • VexiiRiscv generation
        • Software test
        • Simulation
        • Conclusion
    • FPU
      • Plugins architecture
      • Area / Timings options
      • Optimized software
  • Branch
    • BtbPlugin
    • GSharePlugin
    • DecodePlugin
    • BranchPlugin
    • LearnPlugin
  • Memory (LSU)
    • Without L1
    • With L1
      • Prefetching
        • PrefetchRptPlugin
        • performance measurements
      • Hardware Memory coherency
      • Memory system
        • Why Tilelink
        • Efficiency cookbook
  • Debug support
    • Architecture
    • EmbeddedRiscvJtag
  • How to use
    • Dependencies
    • Repo setup
    • Generate verilog
    • Run a simulation
    • Synthesis
    • Other resources
    • Using IntelliJ IDEA
  • Performance / Area / FMax
    • Tuning
    • Critical paths tool
  • SoC
    • MicroSoc
      • Verilog generation
      • Simulation (SpinalSim / Verilator)
      • Adding a custom peripheral
      • Exporting an APB3 bus to the toplevel
      • Adding a custom instruction
    • Litex
VexiiRiscv
  • Search

© Copyright 2023 - 2024, VexiiRiscv.

Built with Sphinx using a theme provided by Read the Docs.

Version: master git~967f1ed 2024-11-19

Other Versions v: master
Languages
en
Branches
master
Downloads
HTML
SingleHTML
PDF