VexiiRiscv
Introduction
Other doc / media / talks
Technicalities
Navigating the code
About VexRiscv (not VexiiRiscv)
Check list
Framework
Dependencies
Scala / SpinalHDL
Plugin
Simple all-in-one example
Negotiation example
Database
Pipeline API
Fetch
FetchPipelinePlugin
PcPlugin
FetchCachelessPlugin
FetchL1Plugin
PrefetcherNextLinePlugin
BtbPlugin
GSharePlugin
HistoryPlugin
Decode
DecodePipelinePlugin
AlignerPlugin
DecoderPlugin
DecodePredictionPlugin
DispatchPlugin
Execute
Introduction
Plugins
infrastructures
ExecutePipelinePlugin
ExecuteLanePlugin
RegFilePlugin
SrcPlugin
RsUnsignedPlugin
IntFormatPlugin
WriteBackPlugin
LearnPlugin
Instructions
IntAluPlugin
BarrelShifterPlugin
BranchPlugin
MulPlugin
DivPlugin
LsuCachelessPlugin
Special
CsrAccessPlugin
CsrRamPlugin
PrivilegedPlugin
PerformanceCounterPlugin
EnvPlugin
Custom instruction
SIMD add
Plugin implementation
VexiiRiscv generation
Software test
Simulation
Conclusion
Load Store Unit (LSU)
Without L1
With L1
Memory coherency
Prefetching
PrefetchRptPlugin
FPU
Plugins architecture
Area / Timings options
Optimized software
Branch Prediction
BtbPlugin
GSharePlugin
DecodePredictionPlugin
BranchPlugin
LearnPlugin
Debug
JTAG
How to use
Dependencies
Repo setup
Generate verilog
Run a simulation
Synthesis / Inferation
Performance / Area / FMax
Tuning
SoC
MicroSoc
Litex
VexiiRiscv
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Other Versions
v: master
Languages
en
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master
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